H8SXSLASH1663R datasheet(166/1504 Pages) RENESAS

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Section 7 Interrupt Controller

Rev. 2.00 Sep. 24, 2008 Page 134 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

IPSETE

R/W

Interrupt Priority Set Enable

Controls the function which automatically assigns the

interrupt priority level of the CPU. Setting this bit to 1

automatically sets bits CPUP2 to CPUP0 by the CPU

interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR).

0: Bits CPUP2 to CPUP0 are not updated automatically

1: The interrupt mask bit value is reflected in bits

CPUP2 to CPUP0

CPUP2

CPUP1

CPUP0

R/(W)*

CPU Priority Level 2 to 0

These bits set the CPU priority level. When the

CPUPCE is set to 1, the CPU priority control function

over the DTC, DMAC and EXDMAC becomes valid and

the priority of CPU processing is assigned in

accordance with the settings of bits CPUP2 to CPUP0.

000: Priority level 0 (lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (highest)

Note:

When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits

cannot be modified.

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