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H8SX/1663R データシート(PDF) 163 Page - Renesas Technology Corp |
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H8SX/1663R データシート(HTML) 163 Page - Renesas Technology Corp |
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163 / 1504 page  Section 7 Interrupt Controller Rev. 2.00 Sep. 24, 2008 Page 131 of 1468 REJ09B0412-0200 7.2 Input/Output Pins Table 7.1 shows the pin configuration of the interrupt controller. Table 7.1 Pin Configuration Name I/O Function NMI Input Nonmaskable External Interrupt Rising or falling edge can be selected. IRQ11 to IRQ0 Input Maskable External Interrupts Rising, falling, or both edges, or level sensing, can be independently selected. 7.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) • CPU priority control register (CPUPCR) • Interrupt priority registers A to O, Q, and R (IPRA to IPRO, IPRQ, and IPRR) • IRQ enable register (IER) • IRQ sense control registers H and L (ISCRH, ISCRL) • IRQ status register (ISR) • Software standby release IRQ enable register (SSIER) |
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