H8SXSLASH1663R datasheet(196/1504 Pages) RENESAS

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Section 7 Interrupt Controller

Rev. 2.00 Sep. 24, 2008 Page 164 of 1468

REJ09B0412-0200

to the DTCP and DMAP setting. If the CPU is given priority over the DTC or DMAC, the DTC or

DMAC may not be activated, and the data transfer may not be performed.

(2)

Priority Determination

The DTC activation source is selected according to the default priority, and the selection is not

affected by its mask level or priority level. For respective priority levels, see table 12.1, Interrupt

Sources, DTC Vector Addresses, and Corresponding DTCEs.

(3)

Operation Order

If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the

CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is

selected as the DTC, DMAC or EXDMAC activation source or CPU interrupt source, respective

operations are performed independently.

Table 7.6 lists the selection of interrupt sources and interrupt source clear control by setting the

DTA bit in DMDR of the DMAC, the DTCE bit in DTCERA to DTCERH of the DTC, and the

DISEL bit in MRB of the DTC.

Table 7.6

Interrupt Source Selection and Clear Control

Setting

DMAC

DTC

Interrupt Source Selection/Clear Control

DTA

DTCE

DISEL

DMAC

DTC

CPU

√

[Legend]

√: The corresponding interrupt is used. The interrupt source is cleared.

(The interrupt source flag must be cleared in the CPU interrupt handling routine.)

O: The corresponding interrupt is used. The interrupt source is not cleared.

X: The corresponding interrupt is not available.

*: Don't care.

(4)

Usage Note

The interrupt sources of the SCI, and A/D converter are cleared according to the setting shown in

table 7.6, when the DTC or DMAC reads/writes the prescribed register.

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