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H8SX/1663R データシート(PDF) 208 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 208 Page - Renesas Technology Corp

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Section 8 User Break Controller (UBC)
Rev. 2.00 Sep. 24, 2008 Page 176 of 1468
REJ09B0412-0200
8.3.3
Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD)
BRCRA, BRCRB, BRCRC, and BRCRD are used to specify and control conditions for channels
A, B, C, and D of the UBC.
Bit:
Initial Value:
R/W:
[Legend]
n = Channels A to D
15
−
0
R/W
14
−
0
R/W
13
CMFCPn
0
R/W
12
−
0
R/W
11
CPn2
0
R/W
8
−
0
R/W
10
CPn1
0
R/W
9
CPn0
0
R/W
7
−
0
R/W
6
−
0
R/W
5
IDn1
0
R/W
4
IDn0
0
R/W
3
RWn1
0
R/W
0
−
0
R/W
2
RWn0
0
R/W
1
−
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
14
0
0
R/W
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
13
CMFCPn
0
R/W
Condition Match CPU Flag
UBC break source flag that indicates satisfaction of a
specified CPU bus cycle condition.
0: The CPU cycle condition for channel n break
requests has not been satisfied.
1: The CPU cycle condition for channel n break
requests has been satisfied.
12
0
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
11
10
9
CPn2
CPn1
CPn0
0
0
0
R/W
R/W
R/W
CPU Cycle Select
These bits select CPU cycles as the bus cycle break
condition for the given channel.
000: Break requests will not be generated.
001: The bus cycle break condition is CPU cycles.
01x: Setting prohibited
1xx: Setting prohibited
8
7
6
0
0
0
R/W
R/W
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.



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