H8SXSLASH1663R datasheet(210/1504 Pages) RENESAS

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Section 8 User Break Controller (UBC)

Rev. 2.00 Sep. 24, 2008 Page 178 of 1468

REJ09B0412-0200

8.4

Operation

The UBC does not detect condition matches in standby states (sleep mode, all module clock stop

mode, software standby mode, deep software standby, and hardware standby mode).

8.4.1

Setting of Break Control Conditions

1. The address condition for the break is set in break address register n (BARn). A mask for the

address is set in break address mask register n (BAMRn).

2. The bus and break conditions are set in break control register n (BRCRn). Bus conditions

consist of CPU cycle, PC break, and reading. Condition comparison is not performed when the

CPU cycle setting is CPn

= B'000, the PC break setting is IDn = B'00, or the read setting is

RWn

= B'00.

3. The condition match CPU flag (CMFCPn) is set in the event of a break condition match on the

corresponding channel. These flags are set when the break condition matches but are not

cleared when it no longer does. To confirm setting of the same flag again, read the flag once

from the break interrupt handling routine, and then write 0 to it (the flag is cleared by writing 0

to it after reading it as 1).

[Legend]

= Channels A to D

8.4.2

PC Break

1. When specifying a PC break, specify the address as the first address of the required instruction.

If the address for a PC break condition is not the first address of an instruction, a break will

never be generated.

2. The break occurs after fetching and execution of the target instruction have been confirmed. In

cases of contention between a break before instruction execution and a user maskable interrupt,

priority is given to the break before instruction execution.

3. A break will not be generated even if a break before instruction execution is set in a delay slot.

4. The PC break condition is generated by specifying CPU cycles as the bus condition in break

control register n (BRCRn.CPn0

= 1), PC break as the break condition (IDn0 = 1), and read

cycles as the bus-cycle condition (RWn0

= 1).

[Legend]

= Channels A to D

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