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データシートサーチシステム |
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データシートサーチシステム |
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H8SX/1663R データシート(PDF) 217 Page - Renesas Technology Corp |
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H8SX/1663R データシート(HTML) 217 Page - Renesas Technology Corp |
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217 / 1504 page  Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 185 of 1468 REJ09B0412-0200 • The bus start (BS) and read/write (RD/WR) signals can be output. A block diagram of the bus controller is shown in figure 9.1. Address selector Area decoder Internal bus control unit Internal data bus Internal bus control signals External bus control unit External bus arbiter Internal bus arbiter CPU address bus CS7 to CS0 WAIT BREQ BACK BREQO DTC address bus EXDMAC address bus CPU bus acknowledge signal DTC bus acknowledge signal CPU bus request signal DTC bus request signal EXDMAC bus acknowledge signal EXDMAC bus request signal External bus control signals Control registers ABWCR ASTCR WTCRA WTCRB RDNCR CSACR IDLCR BCR1 BCR2 RTCNT RTCOR ENDIANCR SRAMCR BROMCR MPXCR [Legend] ABWCR: ASTCR: WTCRA: WTCRB: RDNCR: CSACR: IDLCR: BCR1: BCR2: ENDIANCR: Bus width control register Access state control register Wait control register A Wait control register B Read strobe timing control register CS assertion period control register Idle control register Bus control register 1 Bus control register 2 Endian control register SRAMCR: BROMCR: MPXCR: DRAMCR: DRACCR: SDCR: REFCR: RTCNT: RTCOR: SRAM mode control register Burst ROM interface control register Address/data multiplexed I/O control register DRAM control register DRAM access control register Synchronous DRAM control register Refresh control register Refresh timer counter Refresh time constant register DMAC address bus DMAC bus acknowledge signal DMAC bus request signal DRAMCR DRACCR SDCR REFCR Refresh timer Figure 9.1 Block Diagram of Bus Controller |
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