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H8SX/1663R データシート(PDF) 218 Page - Renesas Technology Corp |
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H8SX/1663R データシート(HTML) 218 Page - Renesas Technology Corp |
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218 / 1504 page  Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 186 of 1468 REJ09B0412-0200 9.2 Register Descriptions The bus controller has the following registers. • Bus width control register (ABWCR) • Access state control register (ASTCR) • Wait control register A (WTCRA) • Wait control register B (WTCRB) • Read strobe timing control register (RDNCR) • CS assertion period control register (CSACR) • Idle control register (IDLCR) • Bus control register 1 (BCR1) • Bus control register 2 (BCR2) • Endian control register (ENDIANCR) • SRAM mode control register (SRAMCR) • Burst ROM interface control register (BROMCR) • Address/data multiplexed I/O control register (MPXCR) • DRAM control register (DRAMCR) • DRAM access control register (DRACCR) • Synchronous DRAM control register (SDCR) • Refresh control register (REFCR) • Refresh timer counter (RTCNT) • Refresh time constant register (RTCOR) |
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