H8SXSLASH1663R datasheet(262/1504 Pages) RENESAS

262 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 230 of 1468

REJ09B0412-0200

9.5.3

Chip Select Signals

This LSI can output chip select signals (

CS0 to CS7) for areas 0 to 7. The signal outputs low when

the corresponding external address space area is accessed. Figure 9.9 shows an example of

CSn (n

= 0 to 7) signal output timing.

Enabling or disabling of

CSn signal output is set by the port function control register (PFCR). For

details, see section 13.3, Port Function Controller.

In on-chip ROM disabled extended mode, pin

CS0 is placed in the output state after a reset. Pins

CS1 to CS7 are placed in the input state after a reset and so the corresponding PFCR bits should

be set to 1 when outputting signals

CS1 to CS7.

In on-chip ROM enabled extended mode, pins

CS0 to CS7 are all placed in the input state after a

reset and so the corresponding PFCR bits should be set to 1 when outputting signals

CS0 to CS7.

The PFCR can specify multiple

CS outputs for a pin. If multiple CSn outputs are specified for a

single pin by the PFCR,

CS to be output are generated by mixing all the CS signals. In this case,

the settings for the external bus interface areas in which the

CSn signals are output to a single pin

should be the same.

Figure 9.10 shows the signal output timing when the

CS signals to be output to areas 5 and 7 are

output to the same pin.

Bus cycle

External address of area n

Address bus

CSn

Figure 9.9

CSn Signal Output Timing (n = 0 to 7)

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