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H8SX/1663R データシート(PDF) 291 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 291 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 259 of 1468
REJ09B0412-0200
9.7.4
Basic Timing
(1)
2-State Access Space
Figure 9.25 shows the bus timing when the byte control SRAM space is specified as a 2-state
access space.
Data buses used for 16-bit access space is the same as those in basic bus interface. No wait cycles
can be inserted.
B
φ
Address
D15 to D8
D7 to D0
High level
D15 to D8
D7 to D0
Bus cycle
CSn
AS
RD
LUB
LLB
DACK or EDACK
BS
RD/
WR
RD
RD/
WR
T
1
T
2
Note: n = 0 to 7
Valid
Valid
Read
Write
Valid
Valid
Figure 9.25 16-Bit 2-State Access Space Bus Timing



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