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H8SX/1663R データシート(PDF) 293 Page - Renesas Technology Corp |
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H8SX/1663R データシート(HTML) 293 Page - Renesas Technology Corp |
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293 / 1504 page  Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 261 of 1468 REJ09B0412-0200 9.7.5 Wait Control The bus cycle can be extended for the byte control SRAM interface by inserting wait cycles (Tw) in the same way as the basic bus interface. (1) Program Wait Insertion From 0 to 7 wait cycles can be inserted automatically between T2 cycle and T3 cycle for the 3- state access space in area units, according to the settings in WTCRA and WTCRB. (2) Pin Wait Insertion For 3-state access space, when the WAITE bit in BCR1 is set to 1, the corresponding DDR bit is cleared to 0, and the ICR bit is set to 1, wait input by means of the WAIT pin is enabled. For details on DDR and ICR, refer to section 13, I/O Ports. Figure 9.27 shows an example of wait cycle insertion timing. |
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