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H8SX/1663R データシート(PDF) 309 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 309 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 277 of 1468
REJ09B0412-0200
9.9.9
Extension of Chip Select (
CS) Assertion Period
In the address/data multiplexed interface, the extension cycles can be inserted before and after the
bus cycle. For details, see section 9.6.6, Extension of Chip Select (
CS) Assertion Period.
Figure 9.35 shows an example of the chip select (
CS) assertion period extension timing.
T
ma1
T
ma2
T
2
T
t
T
1
T
h
B
φ
Address bus
D15 to D0
D15 to D0
Address cycle
Bus cycle
Data cycle
CSn
LHWR
LLWR
AH
RD
DACK or EDACK
BS
RD/
WR
Note: n = 3 to 7
Address
Read data
Address
Write data
Read
Write
Figure 9.35 Chip Select (
CS) Assertion Period Extension Timing in Data Cycle



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