H8SXSLASH1663R datasheet(310/1504 Pages) RENESAS

部品番号	H8SX/1663R

部品情報	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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メーカー	RENESAS [Renesas Technology Corp]

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 278 of 1468

REJ09B0412-0200

When consecutively reading from the same area connected to a peripheral LSI whose data hold

time is long, data outputs from the peripheral LSI and this LSI may conflict. Inserting the chip

select assertion period extension cycle after the access cycle can avoid the data conflict.

Figure 9.36 shows an example of the operation. In the figure, both bus cycles A and B are read

access cycles to the address/data multiplexed I/O space. An example of the data conflict is shown

in (a), and an example of avoiding the data conflict by the

CS assertion period extension cycle in

(b).

Address bus

Data bus

Bus cycle A

Bus cycle B

(a) Without

CS assertion period extension cycle (CSXTn = 0)

(b) With

CS assertion period extension cycle (CSXTn = 1)

Data hold time is long.

Data conflict

Address bus

Data bus

Bus cycle A

Bus cycle B

Figure 9.36 Consecutive Read Accesses to Same Area

(Address/Data Multiplexed I/O Space)

H8SX/1663R データシート(PDF) 310 Page - Renesas Technology Corp