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H8SX/1663R データシート(PDF) 311 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 311 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 279 of 1468
REJ09B0412-0200
9.9.10
DACK and EDACK Signal Output Timing
For DMAC or EXDMAC single address transfers, the
DACK and EDACK signal assert timing
can be modified by using bits DKC and EDKC in BCR1.
Figure 9.37 shows the
DACK and EDACK signal output timing. Setting the DKC bit or the
EDKC bit to 1 asserts the
DACK or EDACK signal a half cycle earlier.
T
ma1
T
ma2
T
2
T
1
B
φ
DKC, EDKC = 0
DKC, EDKC = 1
Address bus
D15 to D0
D15 to D0
Address cycle
Data cycle
CSn
RD
AH
RD
DACK or
EDACK
BS
RD/
WR
Note: n = 3 to 7
Address
Read data
RDNn = 0
RDNn = 1
Address
Read
data
Figure 9.37
DACK and EDACK Signal Output Timing



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