H8SXSLASH1663R datasheet(146/1504 Pages) RENESAS

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Section 6 Exception Handling

Rev. 2.00 Sep. 24, 2008 Page 114 of 1468

REJ09B0412-0200

6.2

Exception Sources and Exception Handling Vector Table

Different vector table address offsets are assigned to different exception sources. The vector table

addresses are calculated from the contents of the vector base register (VBR) and vector table

address offset of the vector number. The start address of the exception service routine is fetched

from the exception handling vector table indicated by this vector table address.

Table 6.2 shows the correspondence between the exception sources and vector table address

offsets. Table 6.3 shows the calculation method of exception handling vector table addresses.

Table 6.2

Exception Handling Vector Table

Vector Table Address Offset*

Exception Source

Vector Number

Normal Mode*

Advanced, Middle*

Maximum*

2 Modes

Reset

H'0000 to H'0001

H'0000 to H'0003

H'0002 to H'0003

H'0004 to H'0007

H'0004 to H'0005

H'0008 to H'000B

Reserved for system use

H'0006 to H'0007

H'000C to H'000F

Illegal instruction

H'0008 to H'0009

H'0010 to H'0013

Trace

H'000A to H'000B

H'0014 to H'0017

Reserved for system use

H'000C to H'000D

H'0018 to H'001B

Interrupt (NMI)

H'000E to H'000F

H'001C to H'001F

H'0010 to H'0011

H'0020 to H'0023

H'0012 to H'0013

H'0024 to H'0027

H'0014 to H'0015

H'0028 to H'002B

Trap instruction

(#0)

(#1)

(#2)

(#3)

H'0016 to H'0017

H'002C to H'002F

CPU address error

H'0018 to H'0019

H'0030 to H'0033

DMA address error*

H'001A to H'001B

H'0034 to H'0037

UBC break interrupt

H'001C to H'001D

H'0038 to H'003B

Reserved for system use



H'001E to H'001F



H'0022 to H'0023

H'003C to H'003F



H'0044 to H'0047

Sleep interrupt

H'0024 to H'0025

H'0048 to H'004B

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