H8SXSLASH1663R datasheet(240/1504 Pages) RENESAS

部品番号	H8SX/1663R

部品情報	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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メーカー	RENESAS [Renesas Technology Corp]

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 208 of 1468

REJ09B0412-0200

9.2.13

DRAM Control Register (DRAMCR)

DRAMCR specifies the DRAM/SDRAM interface. Rewrite this register while the

DRAM/SDRAM is not accessed.

Bit

Bit Name

Initial Value

R/W

DRAME

R/W

DTYPE

R/W



OEE

R/W

RAST

R/W



CAST

R/W

Bit

Bit Name

Initial Value

R/W

RCDM

R/W

DDS

R/W

EDDS

R/W



R/W

MXC1

R/W

MXC0

R/W

Bit

Bit Name

Initial

Value

R/W

Description

DRAME

R/W

Area 2 DRAM Interface Select

Selects whether or not area 2 is specified as the

DRAM/SDRAM interface. When this bit is set to 1,

select the type of DRAM to be used in area 2 with the

DTYPE bit. When this bit is set to 1, the BCSEL2 bit in

SRAMCR should be set to 0.

0: Basic bus interface or byte-control SRAM interface

1: DRAM/SDRAM interface

DTYPE

R/W

DRAM Select

Selects the type of DRAM to be used in area 2.

0: DRAM is used in area 2

1: SDRAM is used in area 2

13, 12



All 0

Reserved

The initial value should not be changed.

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