H8SXSLASH1663R datasheet(244/1504 Pages) RENESAS

部品番号	H8SX/1663R

部品情報	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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メーカー	RENESAS [Renesas Technology Corp]

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 212 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

MCX1

MCX0

R/W

Multiplexed Address Bit Select

Select the number of bits by which a row address

multiplexed with a column address is shifted to the

lower side. At the same time, these bits select row

address bits compared during a burst access to the

DRAM/SDRAM interface.

00: Shifted by 8 bits

A23 to A8 are compared for 8-bit access space

A23 to A9 are compared for 16-bit access space

01: Shifted by 9 bits

A23 to A9 are compared for 8-bit access space

A23 to A10 are compared for 16-bit access space

10: Shifted by 10 bits

A23 to A10 are compared for 8-bit access space

A23 to A11 are compared for 16-bit access space

11: Shifted by 11 bits

A23 to A11 are compared for 8-bit access space

A23 to A12 are compared for 16-bit access space

Address

RAS

(When RAST = 0)

RAS

(When RAST = 1)

LUCAS, LLCAS

Tc1

Tc2

Row address

Column address

Bus cycle

Figure 9.4

RAS Assertion Timing (Column Address Output for 2 states

in Full Access Mode)

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