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H8SX/1663R データシート(PDF) 245 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 245 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 213 of 1468
REJ09B0412-0200
9.2.14
DRAM Access Control Register (DRACCR)
DRACCR specifies the settings for the DRAM/SDRAM interface. Rewrite this register while the
DRAM/SDRAM is not accessed.
Bit
Bit Name
Initial Value
R/W
15
0
R
14
0
R
13
TPC1
0
R/W
12
TPC0
0
R/W
11
0
R
10
0
R
9
RCD1
0
R/W
8
RCD0
0
R/W
Bit
Bit Name
Initial Value
R/W
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15, 14
All 0
R
Reserved
The initial value should not be changed.
13
12
TPC1
TPC0
0
0
R/W
R/W
Precharge Cycle Control
Select the number of RAS precharge cycles on a
normal access and a refresh cycle.
00: One cycle
01: Two cycles
10: Three cycles
11: Four cycles
11, 10
All 0
R
Reserved
The initial value should not be changed.
9
8
RCD1
RCD0
0
0
R/W
R/W
RAS-CAS Wait Control
Select the number of wait cycles inserted between
RAS
and
CAS cycles.
00: No wait cycle inserted
01: One wait cycle inserted
10: Two wait cycles inserted
11: Three wait cycles inserted
7 to 0
All 0
R
Reserved
The initial value should not be changed.



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